module mealy(output z, input x, input clock); 
   
   wire r2so; 
   wire s2r;
   
   registro registrostato(r2so, s2r, 1'b1, clock); 

   sigma rete_sigma(s2r,r2so,x);
   omega rete_omega(z,  r2so,x);
   
   
endmodule