module prova_mealy();

   wire z; 
   reg  x;
   reg  clock; 

   mealy reteDiMealy(z, x, clock); 


   always
     begin
	if(clock==0) 
	  #2 clock=1;
	else 
	  #1 clock=0;
     end

   initial 
     begin
	$dumpfile("mealy.vlc");
	$dumpvars;

	x = 0; 
	#10 x = 1; 
	#10 x = 0; 
	#10 x = 1; 

	#10 $finish; 

     end
endmodule