module commutatore(output z, input x, input y, input alpha); 

   wire notalpha;
   wire t1;
   wire t2;
   wire res;
   
   
   not(notalpha,alpha);
   and(t1,notalpha,x);
   and(t2,alpha,y);

   or(res,t1,t2);

   assign #2 z = res;
   
endmodule