module memoria # (parameter N=6, M=32) ( 
  output reg [M-1:0] data_out,
  input clock, 
  input beta,
  input [N-1:0] address, 
  input [M-1:0] data_in
); 

  reg [M-1:0]mem_bank[2**N-1:0];
  reg [N:0]i; 

  initial
    begin
       for(i=0; i<2**N; i=i+1) 
	 mem_bank[i]=0;
    end
   
   always @ (posedge clock) 
     begin
	if(beta)
	  mem_bank[address] = data_in; 
     end
   
   always @ (negedge clock)
     begin
	data_out = mem_bank[address]; 
     end
endmodule