`timescale 1ns / 1ps

module prova_mem();

`define IN  4
`define N  32

  wire [`N-1:0]out0;
  reg beta; 
  reg clock; 
  reg [`IN-1:0]addr;
  reg [`N-1:0]in0;

  memoria #(`IN,`N) memoria(out0,clock,beta,addr,in0);

   always
   begin
     if(clock) 
	 #5 clock = ~clock;
     else
	 #10 clock = ~clock; 
   end

  initial
  begin
    $dumpfile("prova_mem.vcd");
    $dumpvars(1,prova_mem);

    clock = 0; 
    beta = 0; 
    addr = 0; 

    #10 in0 = 127;
    #10 beta = 1; 
    #12 beta = 0; 
    #10 addr = addr+1;
    #10 in0 = 255; 
    #10 beta = 1; 
    #10 beta = 0; 
  
    #20 $finish;
  
  end

endmodule